1. Field of the Invention
The present invention relates to a multi-input differential amplifier circuit having two or more pairs of positive and negative input terminals.
2. Description of the Related Art
In a differential amplifier circuit, particularly a multi-input type differential amplifier circuit having two or more pairs of positive and negative input terminals, use is made of a configuration in which an input dynamic range is broadened by connecting drains of transistors configuring a positive side input element to a common node, connecting drains of transistors configuring a negative side input element to another common node, and supplying an operating current by a different current source for every differential pair. A multi-input type differential amplifier circuit having such a configuration was disclosed in Japanese Unexamined Patent Publication (Kokai) No. 9-93052.
FIG. 49 is a circuit diagram of an example of the multi-input type differential amplifier circuit disclosed in Japanese Unexamined Patent Publication (Kokai) No. 9-93052. As illustrated, in this multi-input type differential amplifier circuit, n number of differential pairs are configured by MOS transistors MI01, . . . , MI0n and MI11, . . . , MI1n. The gates of the transistors MI01, . . . , MI1n configure the positive side input terminals, while the gates of the transistors MI01, . . . , MI0n configure the negative side input terminals. The drains of the positive side transistors are connected to a common negative node NDN, while the drains of the negative side transistors are connected to a common positive node NDp. The node NDN is connected to w a supply line of a power supply voltage VDD via a load resistor circuit RL1, while the node NDP is connected to the supply line of the power supply voltage VDD via a load resistor circuit RL0. The sources of the two transistors such as the transistors MI01 and MI11, configuring each differential pair are connected to a common node, while operating currents are supplied to these nodes by different current sources. For example, the sources of the pair transistors MI01 and MI11 are connected to a node VS1, while the sources of the pair transistors MI0nn and MI1n are connected to a node VSn. An operating current ID1 is supplied to the node VS1 by a current source IS1, while an operating current IDn is supplied to the node VSn by a current source ISn.
FIG. 50 is a view of an example of the multi-input type differential amplifier circuit shown in FIG. 49. Note that, here, a so-called 4-terminal input differential amplifier circuit having two positive and negative input terminals is shown.
As illustrated, in this differential amplifier circuit, an output load circuit is configured by a current mirror circuit configured by p-channel MOS transistors ML0 and ML1. Namely, both of the sources of the transistors ML0 and ML1 are connected to the supply line of the power supply voltage VDD, the gates of these transistors are connected to each other, and a connection point thereof is connected to the drain of the transistor ML0. The drain of the transistor ML0 is connected to the common node NDp of the drains of the positive side transistors MI01 and M02, while the drain of the transistor ML01 is connected to the common node NDN of the negative side transistors MI11 and MI12.
Further, the current source for supplying the operating current to each differential pair is configured by n-channel MOS transistors MS1 and MS2 to the gate of which a predetermined bias voltage is applied. For example, the drain of the transistor MS1 is connected to the node VS1, while the drain of the transistor MS2 is connected to the node VS2. A bias voltage VBIAS is input to the gates of these transistors MS1 and MS2. Note that the bias voltage VBIAS is created by the current source IS0 and the nMOS transistor MS0.
The node ND, and the node NDN configure a non-inverted output terminal DFO(+) and an inverted output terminal DFO(xe2x88x92) of the differential amplifier circuit. The output signal of the inverted output terminal DFO(xe2x88x92) is input to a push-pull output stage configured by transistors PT1 and NT1 via a source follower configured by transistors ML2 and MS3. The output signal of the source follower is amplified by the push-pull output stage and output to the output terminal OUT. Note that a resistance element R1 and a capacitor C1 forming a phase compensation circuit are connected in series between the inverted output terminal DFO(xe2x88x92) of the differential amplifier circuit and the output terminal OUT of the push-pull output stage.
FIG. 51 is a view of an example of another configuration of the multi-input type differential amplifier circuit. As illustrated, the differential amplifier circuit of the present example is a 6-terminal input differential amplifier circuit configured by three differential pairs. The configuration of the circuit of the example is substantially the same as the 4-terminal input differential amplifier circuit shown in FIG. 50 except that it has three differential pairs. Note that in this circuit, the current amplification rates of the transistors configuring the differential pairs are set to different values, therefore an amplification signal weighted with respect to the input signal is obtained.
When the current amplification rate of transistors MI01 and MI11 is xcex21, the current amplification rate of the transistors MI02 and MI12 is xcex22, the current amplification rate of transistors MI03 and MI13 is xcex23, and the ratio of the current amplification rates of the transistors MS1, MS2, and MS3 is xcex21:xcex22:xcex23, the differential signal input to each differential pair is weighted in accordance with the current amplification rate of the transistors configuring each differential pair, thus the amplification signal is obtained.
In the multi-input type differential amplifier circuit mentioned above, when the differential amplifier circuit is used by supplying a negative feedback between the input and the output, the usual differential amplifier circuit having only one pair of positive and negative input terminals operates based on a state where the voltage of the positive side input terminal and the voltage of the negative side input terminal are equal (virtual ground), but in contrast, in a multi-input type differential amplifier circuit, the voltage of the positive side input terminal and the voltage of the negative side input terminal do not have to be equal for every pair, so it operates based on a state where the summation of voltages of the positive side input terminals and the summation of voltages of the negative side input terminals become equal.
Namely, a multi-input type differential amplifier circuit must operate even in a case where voltages of the positive side input terminal and the negative side input terminal are different for every differential pair. When looking at the drain voltage of the transistor configuring a current source for supplying an operating current to a differential input pair, however, this becomes the output voltage of an OR type source follower circuit using positive and negative input terminals as two input terminals. For this reason, when there is a difference between the voltages of the positive and negative input terminals of more than the threshold voltage of the transistors configuring an input element, the output voltage of the OR type source follower circuit becomes a voltage shifted from the gate voltage of the transistor which is further turned on between the two transistors configuring the input element by the value of the threshold voltage Vth, so a voltage required for turning on the related transistor will not be supplied between the gate and the source of the transistor configuring the other input element.
As a result, when the voltages of the positive and negative input terminals are separated from each other more than the value of the threshold voltage Vth of the transistors configuring the input element, a state where a current regulated by a constant current source flows through the transistors configuring one input element, while no current flows through the transistors configuring the other input element is exhibited, so there is the disadvantage that it no longer appears as a change of the current. This means that the voltage change of the node to which the drains of the transistors configuring the positive side input element, that is, the output of the differential input circuit, are commonly connected and the other node to which the drains of the transistors configuring the negative side input element are commonly connected, that is, the inverted output terminal and the non-inverted output terminal of the differential input circuit, deviates from the output voltage expected from a multi-input differential amplifier circuit.
Note that, in the multi-input type differential amplifier circuit mentioned above, in the case of an operational amplifier circuit configured by supplying negative feedback between the input and the output, the voltage difference between the positive and negative output nodes of the differential input circuit is small, and each voltage becomes substantially constant.
On the other hand, in the case of a comparison and judgment circuit using a multi-input differential amplifier circuit without supplying a negative feedback, at least one of the positive and negative output nodes of the differential input circuit has amplitude, therefore the voltage conditions under which transistors configuring all input elements and constant current sources have a linear characteristic become further narrower. For this reason, there is the disadvantage that, in the case of the comparison and judgment circuit, the expected characteristics cannot be obtained by just an above multi-input type differential amplifier circuit supplying operating currents by different current sources for every differential input.
An object is to provide a multi-input type differential amplifier circuit capable of maintaining the linear characteristic of the input voltage and the output voltage even in a case where there is a difference between the input voltages of the differential input terminals of more than the threshold voltage of the transistors configuring the differential pair and capable of enhancing the dynamic range and the linear characteristic.
To achieve the above object, a multi-input type differential amplifier circuit of the present invention is a multi-input differential amplifier circuit having at least two pairs of positive and negative input terminals, comprising at least two differential pairs each comprising a first and a second transistor with control gates which are respectively connected to said positive and negative input terminals, with one terminals which are connected to first and second output terminals, and with other terminals which are connected to current supply nodes via first and second resistors, and at least two current sources for supplying operating currents to said current supply nodes in said differential pairs, first and second load circuits being connected between said first and second output terminals and a supply line of a first power supply voltage.
Further, a multi-input type differential amplifier circuit of the present invention has at least two differential pairs each comprising a first and a second transistor with control gates which are respectively connected to said positive and negative input terminals, with one terminals which are connected to first and second output terminals, and with other terminals which are connected to current supply nodes via third and fourth resistors, and at least two current sources for supplying operating currents to said current supply nodes in said differential pairs, first and second load circuits being connected between said first and second output terminals and a supply line of a first power supply voltage, a predetermined bias voltage being applied to the control gates of said third and fourth transistors.
Further, in the present invention, preferably said current sources for supplying the operating currents to said each differential pair are each configured by a transistor to the control gate of which the predetermined bias voltage is applied, with one terminal which is connected to said current supply node, and with another terminal which is connected to the supply line of a second power supply voltage.
Further, in the present invention, preferably, said first and second load circuits are configured by resistors connected between said first and second output terminals and the supply line of said first power supply voltage or said first and second load circuits are configured by first and second load configuring transistors which are connected between said first and second output terminals and the supply line of said first power supply voltage and configure a current mirror circuit.